One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, have expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
FIG. 1 illustrates a cross-section of a conventional BGA integrated circuit (IC) package structure 10 having a die or flip chip 16 which is inverted and bonded to a carrier substrate 12, such as a printed circuit board (PCB), for example. Multiple solder balls 14 are attached to the carrier substrate 12 to facilitate electrical connection of the carrier substrate 12 to higher-order electronic structures (not shown). Fabrication of the flip chip 16 is begun by forming multiple bonding pads 18 on the surface of a chip substrate 17, in electrical contact with integrated circuits (not shown) previously fabricated on the chip substrate 17. A solder bump 20 is then bonded to each of the bonding pads 18. Each of the solder bumps 20 is typically spherical in configuration and extends through a passivation layer (not shown) formed on the surface of the chip substrate 17. A tin oxide layer (not shown) may coat the surface of each solder bump 20.
In assembly of the IC package structure 10, the flip chip 16 is subjected to a re-flow temperature of typically about 320° C. to re-flow the lead solder bumps 20 on the chip substrate 17. The flip chip 16 is then inverted and the solder bumps 20 are bonded with respective bond pads (not shown) on the carrier substrate 12. The re-flow heat partially melts the tin oxide layer (not shown) on the solder bumps 20 and bonds the underlying lead solder bumps 20 to the carrier substrate 12.
In an underfill process, an adhesive material 22, such as an epoxy, for example, is provided between the carrier substrate 12 and the chip substrate 17. The hardened adhesive material 22, which typically has a high Young's modulus, attaches the flip chip 16 to the carrier substrate 12 and protects the solder bumps 20 from cracking in the finished IC package structure 10. The material characteristics of the adhesive material 22 are important for optimum adhesion of the flip chip 16 to the carrier substrate 12 and thermal insulation.
After the flip chip 16 is attached to the carrier substrate 12 and the adhesive material 22 is injected between the flip chip 16 and the carrier substrate 12, the IC package structure 10 is subjected to a variety of tests such as, for example, reliability tests in which the IC package structure 10 is heated to test the reliability of electrical interconnections between the flip chip 16 and the carrier substrate 12. Furthermore, during functioning of the flip chip 16 in an electronic apparatus (not shown) of which the flip chip 16 is a part, heat is generated between the flip chip 16 and the carrier substrate 12. This causes the flip chip 16 and the carrier substrate 12 to thermally expand with respect to each other. Because they have different coefficients of thermal expansion (CTE), however, the flip chip 16 and the carrier substrate 12 expand at different rates. Consequently, the resulting stress placed upon the solder bumps 20 and adhesive material 22 frequently causes interfacial delamination of the adhesive material 22. This results in lower reliability of the flip chip 16.
Accordingly, a novel chip packaging structure and method is needed for improving chip reliability by relieving physical stresses and facilitating dissipation of heat from a flip chip during flip chip testing and functioning.
An object of the present invention is to provide a novel IC chip package structure for improving chip reliability.
Another object of the present invention is to provide a novel IC chip package structure in which delamination stress caused by different coefficients of thermal expansion (CTE) between a flip chip and a carrier substrate is reduced.
Still another object of the present invention is to provide a novel IC chip package structure in which multiple concave structures, such as a set of openings or channels or a channel matrix, for example, is/are provided in the backside of an IC flip chip or die to enhance dissipation of heat from the flip chip and reduce stress between the flip chip and a carrier substrate to which the flip chip is bonded.
Yet another object of the present invention is to provide a novel method for reducing delamination stress between an IC flip chip and a carrier substrate in an IC package structure.